China semiconductor terms, defined

The number of wafers a fab can start in a period, normally stated per month. ForSilicon’s public China series reports monthly capacity in kunits on an 8-inch-equivalent basis.

One kunit is 1,000 wafers. A figure of 14,800 kunits per month is 14.8 million wafers per month, which Chinese media write as 1480万片/月.

A common basis for adding up wafers of different diameters: each wafer is converted to the area of an 8-inch (200 mm) wafer. By area, one 12-inch (300 mm) wafer is 2.25 eight-inch wafers. Quote the basis whenever you quote a capacity figure.

The share of installed capacity in use: wafers started divided by the wafers the line could start. Capacity says how much a fab can make; utilization says how much it is making.

A year marked F, such as 2030F, is a forecast. A market-sizing horizon marked E, such as 2022–2030E, ends in estimated years. Read a marked year as a projection, not a reported result.

Capacity located in mainland China, split by who owns the line: Chinese companies, or foreign companies operating fabs in China. ForSilicon’s public series states the ratio between the two for 2030F.

A company that manufactures wafers to other companies’ chip designs and does not sell chips under its own brand.

A company that designs, manufactures, and sells its own chips, running its own wafer fabs and often its own packaging lines.

A chip company that designs and sells devices but buys wafer manufacturing from foundries and packaging from OSATs.

A company that packages and tests chips for other firms. OSATs, along with the packaging lines of IDMs and foundries, buy packaging equipment and materials.

A product split used in fab directories. Memory fabs make DRAM and NAND flash; non-memory fabs make logic, analog, power, sensor, and other devices.

A fab built on a new site with no existing semiconductor line, so buildings, utilities, suppliers, and staff are all assembled from the start.

The term India’s semiconductor incentive programs use for back-end facilities. In practice it covers the same work as an OSAT line.

The tools that process wafers in a fab: lithography, etch, deposition, CMP, clean, furnace, and others. WFE spend is what fabs pay for those tools, and it follows capacity expansion.

The step that prints a circuit pattern on the wafer by exposing a light-sensitive photoresist through a mask.

The step that removes material from selected areas of the wafer, transferring the lithography pattern into the layers beneath.

The step that adds thin films of conducting, insulating, or semiconducting material to the wafer, by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

Polishing the wafer flat between layers with a chemical slurry and a pad. CMP is both a tool category and a consumables market.

Wet or dry steps that remove particles, residues, and metal contamination from the wafer between other process steps.

Thermal process tools that treat batches of wafers at high temperature for oxidation, diffusion, annealing, and low-pressure chemical vapor deposition.

The shift of fab and packaging-line purchases from imported equipment, materials, and components to products made by Chinese suppliers. Also called domestic substitution (国产替代).

The polished disc of single-crystal silicon on which chips are built. Mainstream diameters are 12-inch (300 mm) and 8-inch (200 mm).

A wide-bandgap compound semiconductor used mainly for power devices. ForSilicon tracks 8-inch and 6-inch SiC lines alongside 12-inch and 8-inch silicon.

The term used in China for wide-bandgap materials, chiefly silicon carbide (SiC) and gallium nitride (GaN). Elsewhere they are usually called wide-bandgap semiconductors.

The light-sensitive coating that lithography exposes and develops to form a pattern. Each exposure wavelength needs its own resist chemistry.

High-purity gases used in etch, deposition, doping, and chamber cleaning.

High-purity acids, bases, and solvents used for wafer cleaning, wet etch, and photoresist developing and stripping.

The block of metal or compound that a PVD tool bombards to deposit a thin film on the wafer.

The part that holds a wafer in a process chamber by electrostatic force and controls its temperature during etch or deposition.

Radio-frequency generators and matching networks that create and control the plasma in etch and deposition chambers.

Pumps, valves, gauges, and seals that hold a process chamber at the pressure the step requires.

Packaging methods that connect chips at higher density than wire bonding, including flip chip, wafer-level and fan-out packaging, 2.5D, and 3D integration.

Chips placed side by side on an interposer that routes dense connections between them.

Chips stacked vertically and connected through the stack, for example by through-silicon vias (TSVs).

Joining two wafers or dies with direct copper-to-copper and dielectric-to-dielectric bonds, without solder bumps, which allows a much finer connection pitch.

A small die built to be combined with other dies in one package, instead of putting every function on a single large chip.

Combining dies made on different processes, such as logic, memory, and analog, in one package.

Stacked DRAM dies connected by through-silicon vias and packaged next to a processor, used mainly with AI accelerators.